For this example, we will recreate the circuit from Glenn's Verilog tutorial, this time in the schematic editor.
If you have not already done so, I recommend reading his example first. It is available here.

This schematic project will only need two files: schematic and constraints.

First, start a new project.

Source type is one key difference between a schematic and verilog project. We can change this later but here we are...
Select schematic under top-level source type.


On the next screen, select the device settings for the Mojo.


Next, add a source file. Select Schematic.


Add another source, this will be the 'Implementation constraints file'.


Since we will be using the same pins on the Mojo, just copy and paste the following lines into the new constraints file.


Now for the schematic.

To create the same function from Glenn's tutorial, we will need a few components.
An input buffer, an output buffer, and an inverter gate.

To find these, open the Symbols tab.
Select IO category to find 'ibuf' and 'obuf'.


Place one of each on the schematic sheet.

Then select the Logic category and choose the 'inv' symbol.


Put one of these between the ibuf and the obuf on the schematic.

Next, we will connect these symbols to make a working circuit.
Use the 'add wire' tool and draw wires between the symbols.


Now we make two last connections for input and output.

Select the 'Add IO Marker' tool and click on the open ends of the ibuf and obuf symbols.


Right-click the input marker and select 'Rename port'.
Call it 'RESET_N'.


Do the same thing for 'LED' on the output buffer.

Be sure to use the exact net names listed in our constraints file.


The last step before compiling will be to enable output to a binary file.
Choose the Design tab and right-click on 'Generate Programming File' in the process list.
Select 'Process Properties'.
Check the box next to 'Create Binary Configuration File'.


Now, if we double-click 'Generate Programming File' our project will soon be ready for programming.

Once complete, we will need to use the Mojo Loader as with Glenn's example.

---

Something more complex

This example will be a bit more complicated but will show some of the tools we can use to draw a circuit.

Let's create a new project.
Add a schematic file and then a constraints file as before.

What should we build?

How about a 'flowing' light effect from the edges to the center of the Mojo's onboard LEDs?
There are eight LEDs so we will need to define more pins.

Copy the following into our constraints file:


That gives us access to all of the LEDs and the button.

So how do we create this thing?

From a programmer's perspective, we might write a for-loop and switch the LEDs on and off at the right time.
We can also do this directly with digital circuits.

I remember that a Johnson counter will fill (set) the bits of a register and then empty (clear) them continuously.

The circuit looks like this:


We will only have to add a few connections to make the flowing effect.

For this circuit, we will need flip-flops and an inverter.
On the Symbols tab, select the Flip_Flop category.

The first entry is 'fd'. It is a simple D type flipflop. That is exactly what we want.
Put four of them on the schematic sheet.


We will also need an inverter, an ibuf and 8 obufs. Add these to the schematic sheet.

<IMG SRC="no connections.png">

Connect the flip-flops and inverter circuit.

<IMG SRC="some connections.png">

Connect the input buffer to the 'C' input of all flip-flops.

<IMG SRC="clock.png">

Now connect the output of the inverter gate to the input of the first flip-flop.

<IMG SRC="feedback.png">

This next part gets a little tricky. Let's connect the obuf symbols.
Assuming your output buffers are lined up horizontally (like the reference circuit), connect the outer pair of buffers to the output of the left-most flipflop.
Wire the next outer buffers to the next flipflop, and so on...


Use the IO Marker tool to add 8 outputs and one input.

<IMG SRC="output buffers j counter.png">

Then, rename the IO markers to match the nets in our constraints file.

At this point we can change the project to generate a binary file as we did before.
Open the Design tab, right-click 'Generate Programming File' and check 'Create Binary Configuration File'
Then double-click 'Generate Programming File' to compile.

<IMG SRC="feedback.png">

Hmm...
There is a problem.
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair.

Don't panic.

What it means is that we have connected our button press to several clock inputs (on the flipflops).
The FPGA has dedicated circuits for that but we are not using them.

We can add the line to our constraints file as suggested at the end of the error, but there is a better option.

Going back to the Symbols tab, find and add to the schematic, a 'bufh' from the 'Clocking_Resources' category.
Select the Options tab, under 'When you click on a branch', make sure 'Select the line segment' option is chosen. This will let us edit the wiring.

Select and remove the connection from the 'ibuf' marked 'RESET_N' away from the 'C' signal going to all four flip-flops.

[img removed clock]

Next connect the 'ibuf' to the input of the 'bufh' object. Finally attached the output of the 'bufh' to the 'C' wiring of the four flip-flops.


That should keep the compiler happy. Return to the Design tab and double-click 'Generate Programming File'.

Upload the binary file, and have fun pressing the button.

You want more?

If you would like to make your circuits automatic (rather than pressing the button), we can also use the on-board oscillator as the clock input.

We'll start by adding this line to the constraints file:


Back in the schematic view, go to the Symbols tab.
Add an 'ibuf' symbol from the IO category.
Then use the IO Marker tool to name the input net to 'CLOCK_IN'.

That gives us a signal from the main oscillator.

You might wonder, at 50MHz, how fast will our circuit go?

We are going to need to step down the clock to be able to see our circuit in action.
Connecting directly won't hurt anything, but the LEDs will always appear to be lit.

To slow the frequency down, we can use counters.
We will use them in the same way 60 ticks on a (time) clock will overflow to a minute... except each of our 'minutes' will be a few million ticks long.

Which counters should we use?

Since we have 16 bit counters readily available, we'll use those.
Two 16-bit counters will divide the signal down by around 4 billion.
We can also tap into one of the lower bits anywhere in those counters to choose a different rate.

Open the Symbols tab.

Add two cr16ce counters from the Counter category.
This type is simple without extra pins.


Buses and signal traffic-

In Verilog, you can use multiple bits, selecting the most significant down to the least significant bit, like this:


In the schematic editor, we can draw a single wire to represent several bits.
These wires are called buses.

All we have to do is label them using a BITS(MSB:LSB) format.

[show renaming a wire]

Be sure to use Labels instead of IO Markers or the compiler will complain later...

Draw a wire out from the first 16 bit counter but not ending anywhere specific.
Use the Label tool and give that wire a name:
I will use A(15:0)


Select the 'Add wire' tool again.
Notice in the options panel, a check box that starts 'Automatically add bus tap between...'.
Check that option.

Next connect the pair of 16 bit counters _starting_ with the clock input of the second counter and ending on the A(15:0) bus.

Label this new wire A(15).


Draw another wire from the second counter output.
Label this as another bus: B(15:0)


Next, remove the 'RESET_N' connection to the 'bufh' object.
We can reconnect 'RESET_N' to the 'clear' input of our new counters.
You will probably want to add an inv logic gate between, otherwise the circuit will only operate while pressing the button.


Draw a wire from the input of the 'bufh' to the B(15:0) bus.
Label this new wire with a bus tap somewhere in the middle of the 16 bit counter.
I will choose B(7).


Now, wire 'CLOCK_IN' ibuf to 'C' of the first 16 bit counter.


To make sure our counters will... count, we have to set 'Clock Enable'.
Under the symbols tab, find and add a 'Constant' from the General category.


Connect the constant to the CE pins of both 16 bit counters.
Constants can be 0, 1 or a number of bits long and the compiler will fit as needed.
All 'F' in hex is just a string of 1's.

Finally, compile the project and upload using Mojo loader.
Don't worry if you see warnings for unconnected nodes, we left quite a few unused from those counters.

What have we done?

Depending on which pins you chose for the counter, we should get a clock to our flowing circuit that is around a couple times per second.

Final thoughts:
Is the schematic tool a 'better' way to program an FPGA?

It is simply another way. Another tool available to use.
I prefer to sketch out circuits before I build them. If I use the schematic editor, I can save myself the step of writing Verilog or VHDL to describe the circuit.
Code is sent to the compiler either way.

You can view the Verilog output in your project folder. It will have a *.vf file extension. I believe VHDL will have another extension.

There are more features available within ISE.
Rather than combining two counters, we can generate a single counter that fits our needs.
We can also generate different clock speeds. Including faster than our on-board oscillator...

You can make connections to a tapped bus signal simply by labeling it properly.
Bus taps are not necessary but can remind you of connections when you look at your circuit later.

There is another aspect of using buses that I did not cover: input and output.
Naming nets with an array-like syntax gives the option of connecting them together.
I will leave those for you to explore.



More info:

Xilinx has a description of the schematic components available on the Mojo.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_scm.pdf

You can find the pin number for the Mojo in the board schematic.
https://embeddedmicro.com/media/wysiwyg/mojo/v3-sch.pdf